zSFP/zSFP+ Module Connector

VCK190 Evaluation Board User Guide (UG1366)
Document ID
UG1366
Release Date
2023-03-17
Revision
1.1 English

[Figure 1, callout 13]

The VCK190 board hosts dual-port zSFP/zSFP+ J287, which accepts zSFP or zSFP+ modules. The following figure shows the zSFP/zSFP+ module connector circuitry typical of the two implementations.

Figure 1. zSFP/zSFP+ Module Connector

The following table lists the zSFP+ module control and status connections.

Table 1. zSFP0- zSFP1 Module Control and Status Connections
zSFP Control/Status Signal Board Connection zSFP Module
SFP0_TX_FAULT Test point J276 High = Fault zSFP0 J287 lower
Low = Normal operation
SFP0_TX_DISABLE Jumper J35 Off = SFP disabled
On = SFP enabled
SFP0_MOD_DETECT Test point J31 High = Module not present
Low = Module present
SFP0_RS0 1 PU R1420/PD R1426 PU R25 = Full RX bandwidth
PD R30 = Reduced RX bandwidth
SFP0_RS1 1 PU R1421/PD R1427 PU R227 = Full RX bandwidth
PD R142 = Reduced RX bandwidth
SFP0_LOS Test point J33 High = Loss of receiver signal
Low = Normal operation
SFP1_TX_FAULT Test point J30 High = Fault zSFP1 J287 upper
Low = Normal operation
SFP1_TX_DISABLE Jumper J32 Off = SFP disabled
On = SFP enabled
SFP1_MOD_DETECT Test point J277 High = Module not present
Low = Module present
SFP1_RS0 1 PU R1428/PD R1431 PU R182 = Full RX bandwidth
PD R190 = Reduced RX bandwidth
SFP1_RS1 1 PU R1429/PD R1432 PU R185 = Full RX bandwidth
PD R202 = Reduced RX bandwidth
SFP1_LOS Test point J278 High = Loss of receiver signal
Low = Normal operation
  1. The RS0/RS1 PU/PD resistors are not populated. There are pull-down resistors built into the SFP/zSFP modules that select the lower bandwidth mode of the module.

For additional information about the enhanced SFP+ module, see the SFF-8431 specification at the SNIA website.

The zSFP connector I2C interfaces are connected to the I2C bus via the TCA9548 I2C multiplexer U214 (see PMC MIO[46:47] I2C0 Bus and PMC MIO[44:45] I2C1 Bus for more details).

The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Xilinx Design Constraints.