When using the Versal adaptive SoC platform-based design flow, you must partition your design between the hardware platform, created in the Vivado tools, and a subsystem, created and incorporated into the platform by the AMD Vitis™ environment. To be successful using this design flow, you must correctly identify the sections of the design to be contained in the platform and the other sections to be incorporated via the Vitis environment. In general, common shared resources are expected to be in the platform, and the specialized components of the design are likely to be incorporated using the Vitis environment.
Common examples of IP contained in the platform include:
- CIPS
- NoC interconnect
- Clocking
- Reset
- Interrupt controllers
The Vitis environment can accept several types of design sources including:
- Packaged BD
- Packaged RTL
- HLS C code
- AI Engine kernel code
The following figure shows an example of the platform-based design flow.
