A high fanout clock spans almost all clock regions of a Versal device or almost an entire SLR of a Versal adaptive SoC stacked silicon interconnect (SSI) technology device. The following figure shows a high fanout clock that spans almost an entire SLR of a Versal adaptive SoC SSI technology device with the XPIO bank BUFGCE driver shown in red. The clock net occupies a vertical routing resource in both SLR0 and SLR1 but only fans out onto the distribution resource in SLR1. Using more than 24 high fanout clocks in a design might cause issues that require upfront planning, such as using Pblocks for logical hierarchies within SLRs or assigning LOC constraints to clock sources in the XPIO banks.
Figure 1. High Fanout Clock Spanning a SLR1 Sourced from an XPIO Bank in
SLR0
