Inserting the clocking elements towards the top level allows for easier clock sharing between modules. This sharing might result in fewer clocking resources needed, which helps in resource utilization, improved maximum clock frequency, and power.
Aside from the module the clocks are created in, clock paths should only drive down into modules. Any paths that go through (down from top and then back to top) can create a delta cycle problem in VHDL simulation that is difficult and time consuming to debug.