In most cases, a low fanout clock is a clock net that is connected to less than 1000 clock pins, which are placed in three or fewer horizontally adjacent clock regions. The clock routing, clock root, and clock distribution are all contained within the localized area.
The placer is expected to identify low fanout clocks but might fail in some cases. This can be caused by design size, device size, or physical XDC constraints, such as a LOC constraint or Pblock, which prevent the placer from placing the loads in a local area. To address this issue, you might need to guide the tool by manually creating a Pblock or modifying the existing physical constraints.
Clocks driven by BUFG_GTs are an example of a low fanout clock. The following figure shows a low fanout clock contained in two clock regions with the BUFG_GT driver shown in green.
