Versal devices include unique IP that require special consideration as follows:
- Include the Control, Interface, and Processing System (CIPS) IP in your
design.
The CIPS IP must be present in every Versal adaptive SoC design, because this IP contains the platform management controller (PMC) required to boot and configure the device. If your design does not include CIPS IP, a post-link/pre-place DRC flags your design. For descriptions of the PMC and PS, see the Versal Adaptive SoC Technical Reference Manual (AM011). For information on CIPS IP, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352). For information on the CPM, see the Versal Adaptive SoC CPM CCIX Architecture Manual (AM016), Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346), and Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).
- Configure the CPM controller, including GT selection, through the
CIPS IP.
For information, see the Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346). The PL access to the PCIe® interface can be configured using the PCI Express® IP through the IP catalog. For more information on PCIe, see the following documents:
- Conduct upfront analysis and early validation of NoC resource
design requirements.
The NoC IP acts as a logical representation of the physical NoC. The Vivado IP integrator aggregates the connectivity and quality of service (QoS) information to form a unified traffic specification. For more information on the NoC and integrated memory controller IP and performance tuning see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
- Use the Advanced I/O Planner to assign the DDR memory controller physical
locations and pins. For more information, see the
Advanced I/O Wizard LogiCORE IP Product Guide
(PG320).
The hardened DDR memory controllers are integrated into the NoC IP. The NoC compiler selects a location for the DDR memory controller while aggregating design requirements. The physical assignments of the DDR memory controllers are adjusted appropriately during implementation.
- Limit SmartConnect to connections requiring AXI4-Lite or when supplementing the NoC when the NoC bandwidth is
fully consumed by the rest of the design or there are not enough NoC ports.
The NoC is the preferred method for moving data throughout the Versal device. For more information, see the SmartConnect LogiCORE IP Product Guide (PG247).
- Use block automation in the IP integrator to assist with
connections between IP and the GTs.
You must use this approach because Versal IP that use GT resources no longer integrate the GT components in the IP. Alternatively, these connections can be stitched manually by configuring, instancing, and connecting the IP directly in the RTL. For an overview of creating a design with GT parent IP, see this link in the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
- Configure the Versal adaptive SoC
transceivers using the Versal adaptive SoC
Transceivers Wizard IP.
Use the Hard Block Planner to assign the physical locations of the GT quads in Versal adaptive SoC designs. For information on the Hard Block Planner, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899). For information on the full GT quad layout and supported configuration options, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).
- Use the Bridge IP to connect custom IP to the Versal adaptive SoC GT quads.
For more information, see this link in the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).