You can validate an AI Engine design using validation techniques similar those used for block validation. One primary difference is that AI Engine is an AXI-interface based IP, making it easier to interface with the different IP in the IP integrator catalog or in Vitis HLS. One common method is to use S2MM and MM2S-based IP to generate DDR memory-based traffic to the AI Engine, retrieve the data from the AI Engine, and transmit the data back to the DDR memory.
The following figure shows the block diagram of an AI Engine design with test harness around it.
Unlike the block IP validation methodology described in the previous section, AI Engine validation includes the following challenges:
- Number of AXI input and out streams from programmable logic to AI Engines.
- Bandwidth of data expected by AI Engine.
For simplicity, AI Engine design validation can be broadly classified into functional validation and performance validation.