The Versal devices include a programmable AXI-interconnecting network on chip (NoC) used for sharing data between IP endpoints in the programmable logic (PL), the control, interface, and processing system (CIPS), and other integrated blocks. NoC is composed of a series of interconnected horizontal NoC (HNoC) and vertical NoC (VNoC) paths, supported by customizable and configurable hardware implemented components. The NoC components comprise NoC master unit (NMU), NoC slave unit (NSU), NoC packet switches (NPS), and NoC Inter-Die Bridge (NIDB). For more information on the architecture and debug and performance analysis features, see this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
The programmable NoC supports end-to-end data protection for AXI4 memory mapped transactions that includes data and address parity and SECDED ECC across the entire NoC packet. The Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019) lists NoC registers used for reporting error status and error management.
Every connection through the NoC has an associated QoS requirement. The details of supported QoS settings and their impact for a particular traffic type is discussed in this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). For guidance on NoC/DDRMC performance tuning, see the Versal Network on Chip/DDR Memory Controller Performance Tuning Tutorial available from the AMD GitHub repository.