When timing closure is difficult to achieve or when you are trying to improve the overall performance of your application, you must review the main characteristics of your design after running synthesis and after any step of the implementation flow. The QoR analysis usually requires that you look at several global and local characteristics at the same time to determine what is suboptimal in the design and the constraints, or which logic structure is not suitable for the target device architecture and implementation tools. The
report_design_analysis command gathers logical, timing, and physical characteristics in a few tables to simplify the QoR root cause analysis.
report_design_analysiscommand does not report on the completeness and correctness of timing constraints.
The following sections only cover timing path characteristics analysis. The Design Analysis report also provides useful information about congestion and design complexity.