Assigning AXI Interfaces to DDR Banks - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
Important: When using more than one DDR interface, Xilinx requires you to specify the DDR memory bank for each kernel/CU, and specify the SLR to place the kernel into. For more information, see Mapping Kernel Ports to Memory and Assigning Compute Units to SLRs.

The following is an example configuration file that specifies the connectivity.sp option, and the v++ command line that connects the input pointer (M_AXI_GMEM0) to DDR bank 0 and the output pointer (M_AXI_GMEM1) to DDR bank 1:

The config_sp.cfg file:

[connectivity] 
sp=apply_watermark_1.m_axi_gmem0:DDR[0] 
sp=apply_watermark_1.m_axi_gmem1:DDR[1]

The v++ command line:

v++ apply_watermark --config config_sp.cfg

You can use the Device Hardware Transaction view to observe the actual DDR Bank communication, and to analyze DDR usage.

Figure 1. Device Hardware Transaction View Transactions on DDR Bank