Build Targets

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The build target of the Vitis™ tool defines the nature and contents of the FPGA binary (.xclbin) created during compilation and linking. There are three different build targets: two emulation targets used for validation and debugging purposes: software emulation and hardware emulation, and the default system hardware target used to generate the FPGA binary (.xclbin) loaded into the Xilinx® device.

Compiling for an emulation target is significantly faster than compiling for the real hardware. The emulation run is performed in a simulation environment, which offers enhanced debug visibility and does not require an actual accelerator card.

Table 1. Comparison of Emulation Flows with Hardware Execution
Software Emulation Hardware Emulation Hardware Execution
Host application runs with a C/C++ or OpenCL™ model of the kernels. Host application runs with a simulated RTL model of the kernels. Host application runs with actual hardware implementation of the kernels.
Used to confirm functional correctness of the system. Test the host / kernel integration, get performance estimates. Confirm that the system runs correctly and with desired performance.
Fastest build time supports quick design iterations. Best debug capabilities, moderate compilation time with increased visibility of the kernels. Final FPGA implementation, long build time with accurate (actual) performance results.