With the RTL kernel generated from a packaged IP into a compiled .xo file you are ready to link the kernel with the target platform and with other kernels and build the system design. Designs with user-managed RTL kernels support hardware emulation builds and hardware builds as described at Build Targets, but do not support software emulation builds, as the RTL kernel does not support inclusion of a C-model.
During the build process the Vitis compiler launches the Vivado Design Suite to automatically place and route the design, and generate the bitstream and the .xclbin file. While the build process is automated by the Vitis compiler, it also offers the opportunity for specifying constraints on complex designs or interactively working in the Vivado tools to help you resolve timing and generate the .xclbin file, as described in Managing Vivado Synthesis and Implementation Results.
The Vivado tools also provide a rich Tcl programming language for scripting and automating elements of the design flow. You can provide Tcl scripts to be run at different stages of the build process for the Vitis compiler or the Vivado tool. These scripts can be enabled for specific steps in the build process using --linkhook Options, or using Vivado properties as explained in --vivado Options.