CED Example Usage - 2022.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2022-05-25
Version
2022.1 English

Download Example Platform

  1. Launch Vivado.
  2. Click Tools > Vivado Store.
  3. Click OK to agree to download open source examples from web.
  4. Select Platform > Versal Extensible Embedded Platform and click the download button on the tool bar.
  5. Click Close after the installation is complete.

    Note: In this example, Versal Extensible Embedded Platform is used. Select the appropriate example design you need.
  6. Click Close after the installation is completed.

    Note: In this example Versal Extensible Embedded Platform is used. Select the appropriate example design you need.

Create CED Example Design

  1. Click File > Project > Open Example.
  2. Select Versal Extensible Embedded Platform in Select Project Template window.
  3. Input project name and project location. Keep Create project subdirectory checked. Click Next.
  4. Select target board in Default Part window. In this example Versal VCK190 Evaluation Platform has been selected. Click Next.

  5. Configure Clocks Settings. You can enable more clocks, update output frequency and define default clock in this view. The default settings are being used in this example.
  6. Configure Interrupt Settings. You can choose how many interrupt should this platform support. 63 interrupts mode will use two AXI_INTC in cascade mode. The default settings are being used in this example.
  7. Configure Memory Settings. By default the example design will only enable DDR4. If you enable LPDDR4, it will enable both DDR4 and LPDDR4. The default settings are being used in this example.
  8. Click Next.
  9. Review the new project summary and click Finish.
  10. After a while, you will see the design example has been generated.

    The generated design instantiated AI Engine, enabled DDR4 controller and connected them to CIPS. It also provides one interrupt controller, three clocks and the associated synchronous reset signals.

Review the Versal Extensible Platform Example Platform Setup

  1. Review the AXI port settings.
    1. In axi_noc_ddr4, S01_AXI to S27_AXI are enabled. SP Tag is set to DDR.

    2. In icn_ctrl_0 and icn_ctrl_1, M01_AXI to M15_AXI are enabled. In icn_ctrl, M03_AXI and M04_AXI are enabled. Memport is set to M_AXI_GP. SP Tag is empty. These ports provide the AXI master interfaces to control PL kernels. In the block diagram, icn_ctrl_0 and icn_ctrl_1 connects to an AXI Verification IP because the AXI SmartConnect IP requires a load. The AXI Verification IP is used here as a dummy.

  2. Review the Clock settings.
    1. In Clock tab, clk_out1, clk_out2, clk_out3 from clk_wizard_0 are enabled with id {0,1,2}, frequency {200 MHz, 100 MHz, 300 MHz}. clk_out1 is the default clock. V++ linker will use this clock to connect the kernel if there aren't any clocks specified in the link configuration. The Proc Sys Reset property is set to the synchronous reset signal associated with each clock.

  3. Review the Interrupt Tab.
    1. In Interrupt tab, In0 to In31 port of xlconcat is enabled.

  4. Review the Simulation Model.
    1. In Vivado Integrated Design Environment (IDE), select the CIPS instance. Check the Block Properties window. In Properties tab, it shows ALLOWED_SIM_MODELS is tlm, and rtl, SELECTED_SIM_MODEL is tlm. This means this block supports two simulation models. In this example, tlm model was selected.

    2. Review the simulation model property for NoC and AI Engine in the block diagram.

Export Hardware XSA

  1. Generate Block Diagram.
    1. Click Generate Block Diagram from Flow Navigator window.

    2. Select Synthesis Options to Global to save generation time. Click Generate button.