Clock and Reset Requirements - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

These clock and reset requirements apply to both software controllable and non-software controllable kernels.

Table 1. Requirements
C/C++/OpenCL C Kernel RTL Kernel
  • C kernel does not require any input from user on clock ports and reset ports. The HLS tool always generates RTL with clock port ap_clk and reset port ap_rst_n.
  • HLS kernels can only have one clock/reset.
  • RTL kernels require at least one clock port, but a kernel can have multiple clocks. The number of clocks that an RTL can have is primarily determined by the number of clocks that the platform supports. Most data center platforms only support two clocks, but most embedded platforms can have multiple clocks.
  • An active-Low reset port can optionally be associated with a clock through the ASSOCIATED_RESET parameter on the clock.