Traditionally, a physical JTAG connection is used to perform hardware debug for Xilinx devices with the Vivado hardware manager. The Vitis unified software platforms also makes use of the Xilinx virtual cable (XVC) for hardware debugging on remote accelerator cards. To take advantage of this capability, the Vitis debugger uses the XVC server, an implementation of the XVC protocol that allows the Vivado hardware manager to connect to a local or remote target device for debug, using the standard Xilinx debug cores like the ILA or the VIO IP.
The Vivado hardware manager, from the Vivado Design Suite or Vivado debug feature, can be running on the target instance or it can be running remotely on a different host. The TCP port on which the XVC server is listening must be accessible to the host running Vivado hardware manager. To connect the Vivado hardware manager to XVC server on the target, the following steps should be followed on the machine hosting the Vivado tools:
- Launch the Vivado debug feature, or the full Vivado Design Suite.
- Select Open Hardware Manager from the
Tasks menu, as shown in the following figure.
- Connect to the Vivado tools
hw_server, specifying a local or remote connection, and the Host name and Port, as shown below.
- Connect to the target instance Virtual JTAG XVC server.
- Select the
debug_bridgeinstance from the Hardware window in the Vivado hardware manager.Specify the probes file (.ltx) for your design adding it to the entry in the Hardware Device Properties window. Adding the probes file refreshes the hardware device, and Hardware window should now show the debug cores in your design.Tip: If the kernel has debug cores as specified in Enabling Kernels for Debugging with Chipscope, the probes file (.ltx) is written out during the implementation of the kernel by the Vivado tool.
- The Vivado hardware manager can now be
used to debug the kernels running on the Vitis
software platform. Arm the ILA cores in your kernels and run your host application.