Design and Target Device Summary - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

All design estimate reports begin with an application summary and information about the target device. The device information is provided in the following section of the report:

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Design Name:             mmult.hw_emu.xilinx_u200_xdma_201830_2
Target Device:           xilinx:u200:xdma:201830.2
Target Clock:            300.000000MHz
Total number of kernels: 1
----------------------------------------------------------------------------

For the design summary, the information provided includes the following:

Target Device
Name of the Xilinx device on the target platform that runs the FPGA binary built by the Vitis compiler.
Target Clock
Specifies the target operating frequency for the compute units (CUs) mapped to the FPGA fabric.