Device Topology - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

In the Vitis core development kit, targeted devices can include Xilinx® MPSoCs or UltraScale+™ FPGAs connected to a processor, such as an x86 host through a PCIe bus, or an Arm processor through an AXI4 interface. The FPGA contains a programmable region that implements and executes a device binary (.xclbin) file that encapsulates hardware kernels as compiled Xilinx object (.xo) files.

The FPGA platform contains one or more global memory banks. The data transfer from the CPU to kernels and from kernels to the CPU happens through these global memory banks. The kernels running in the FPGA can have one or more memory interfaces (m_axi). The connection from the global memory banks to those memory interfaces are configurable and are defined through the Vitis linking options as described in Linking the Kernels. Kernels can also use streaming interfaces (axis) to stream data directly from one kernel to the next. Streaming connections are also managed through v++ linking options.

Multiple kernels (.xo) can be implemented in the PL of the Xilinx device binary (.xclbin), allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances of a kernel is programmable, and determined by linking options specified when building the FPGA binary. For more information on specifying these options, refer to Linking the Kernels.