Embedded Processor Application Acceleration Development Flow - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The following diagram describes the steps needed to build and run an application using Arm® processors and kernels running in programmable logic regions of Versal ACAP, Zynq UltraScale+ MPSoC, and Zynq-7000 SoC devices. The steps are summarized below, and the details of each step can be found throughout this documentation.

Figure 1. Application Development Flow for Versal ACAP and Zynq UltraScale+ MPSoC Devices
PS Application Compilation
Compile the host application to run on the Cortex®-A72 or Cortex-A53 core processor using the GNU Arm cross-compiler to create an ELF file. The host program interacts with kernels in the PL and AI Engine regions of the device. For more information on writing the host application, refer to Developing Applications. For more information on compiling the host application, refer to Building the Host Program.
AI Engine Array (Optional for Versal AI Engine Core series only)
Some Versal ACAP devices incorporate an AI Engine array of very-long instruction word (VLIW) processors with single instruction multiple data (SIMD) vector units that are highly optimized for compute-intensive applications such as 5G wireless and artificial intelligence (AI) applications. AI Engine graphs and kernels are built using Vitis tools such as the aiecompiler and aiesimulator, and can be integrated into the embedded processor application acceleration flow as described in Versal ACAP AI Engine Programming Environment User Guide (UG1076).
PL Kernel Compilation and Linking
PL kernels are compiled for implementation in the PL region of the target platform. PL kernels can be compiled into Xilinx object form (XO) file using the Vitis compiler (v++) or Vitis HLS for C/C++ kernels, or the package_xo command for RTL kernels. For more information on coding kernels, refer to C/C++ Kernels or RTL Kernels.

The Vitis compiler also links the kernel XO files with the hardware platform to create a device executable (.xclbin) for the application. For more information, refer to Building the Device Binary.

Xilinx object (XO) files are linked with the target hardware platform by the v++ --link command to create a device binary file (.xclbin) that is loaded into the Xilinx device on the target platform.

System Package
Use the v++ --package command to gather the required files to configure and boot the system, to load and run the application, including the host application and PL kernel binaries. This step builds the necessary package to run software or hardware emulation and debug, or to create an SD card to run your application on hardware. For more information, refer to Packaging the System.
Running the Application
When running the application, you can run software emulation, hardware emulation, or run on the actual physical accelerator platform. Running the application on embedded processor platforms is different from running on data center accelerator cards. For more information, refer to Running the Application Hardware Build.
  • When the build target is software or hardware emulation, the QEMU environment models the hardware device. The Vitis compiler generates simulation models of the kernels in the device binary and running the application runs in the QEMU model of the system. As described in Build Targets, emulation targets let you build, run, and iterate the design over relatively quick cycles; debugging the application and evaluating performance.
  • When the build target is the hardware system, the target platform is the physical device. The Vitis compiler generates the .xclbin using the Vivado Design Suite to run synthesis and implementation, and resolve timing. Running the application runs your system on the hardware. The build process is automated to generate high quality results; however, hardware-savvy developers can fully leverage the Vivado tools in their design process.