General Settings - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The following figure shows the three settings in the General Settings page.

Figure 1. RTL Kernel Wizard General Settings Page

The following are three settings in the General Settings page.

Kernel Identification

Kernel name
The kernel name. This will be the name of the IP, top-level module name, kernel, and C/C++ functional model. This identifier shall conform to C and Verilog identifier naming rules. It must also conform to Vivado IP integrator naming rules, which prohibits underscores except when placed in between alphanumeric characters.
Kernel vendor
The name of the vendor. Used in the Vendor/Library/Name/Version (VLNV) format described in the Vivado Design Suite User Guide: Designing with IP (UG896).
Kernel library
The name of the library. Used in the VLNV. Must conform to the same identifier rules.

Kernel options

Kernel type
The RTL Kernel wizard currently supports two types of kernels: RTL, and Block Design.
RTL
The RTL type kernel consists of a Verilog RTL top-level module with a Verilog control register module and a Verilog kernel example inside the top-level module.
Block Design
The block design type kernel also delivers a Verilog top-level module, but instead it instantiates an IP integrator block diagram inside of the top-level. The block design consists of a MicroBlaze™ subsystem that uses a block RAM exchange memory to emulate the control registers. Example MicroBlaze software is delivered with the project to demonstrate using the MicroBlaze to control the kernel.
Kernel control interface
There are three types of control interfaces available for the RTL kernel. ap_ctrl_hs, ap_ctrl_chain, and ap_ctrl_none. This defines the hwControlProtocol for the <kernel> tag as described in RTL Kernel XML File.

Clock and Reset options

Number of clocks
Sets the number of clocks used by the kernel. Every RTL kernel has one primary clock called ap_clk and an optional reset called ap_rst_n. All AXI interfaces on the kernel are driven with this clock.

When setting Number of clocks to 2, a secondary clock and optional reset are provided to be used by the kernel internally. The secondary clock and reset are called ap_clk_2 and ap_rst_n_2. This secondary clock supports independent frequency scaling and is independent from the primary clock. The secondary clock is useful if the kernel clock needs to run at a faster or slower rate than the AXI4 interfaces, which must be clocked on the primary clock.

Important: When designing with multiple clocks, proper clock domain crossing techniques must be used to ensure data integrity across all clock frequency scenarios. Refer to UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) for more information.
Has reset
Specifies whether to include a top-level reset input port to the kernel. Omitting a reset can be useful to improve routing congestion of large designs. Any registers that would normally have a reset in the design should have proper initial values to ensure correctness. If enabled, there is a reset port included with each clock. Block Design type kernels must have a reset input.