By default, the python script generates aie_wrapper_ext_tb_ip.tcl and aie_wrapper_ext_tb_proj.tcl along with the wrapper Verilog file as mentioned in the previous section.
There are two ways to proceed based on the existence of a Vivado project:
If you have already created Vivado project, use the IP flow described here. From the Tcl console source the
This Tcl script can be used for generating required
sim_ipc_axisIP. After sourcing the Tcl file you will see hierarchy created under simulation_sources. You can add the required files and directories for your project .
If a Vivado project is not already created, use the project script
aie_wrapper_ext_tb_proj.tclto create one. From a terminal use the following command:
vivado -mode batch -source aie_wrapper_ext_tb_proj.tclNote: To use third party simulators, you need to update the required paths for SIMULATOR_GCC_PATH, SIMULATOR_CLIBS_PATH and INSTALL_BIN_PATH. For more details on how to set the third party simulators, please refer Vivado Design Suite User Guide: Logic Simulation (UG900).
After sourcing aie_wrapper_ext_tb_proj.tcl, the tool will generate the
export_simdirectory with sub-directories and scripts required for use with other simulators. This Tcl script sources the
sim_ipc_axismodules, so you must add any additional required RTL modules and options to the script. You can modify and directly include required RTL the needed script.