Hardware Event Tracing - 2022.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
Release Date
2022.1 English

You can also profile hardware events within the accelerator system composition. Particularly, hardware events on the AXI4 ports of the platform connections and PE interfaces can be captured and presented as a timeline trace.

The picture below is for an example of an accelerator with two CUs, where each CU is a pipeline of three PEs in a chain: mmultincr_10incr_20. As seen in the picture, the rows are topologically organized to show the sequence of events following the order of the pipeline.

The picture show the execution of a single compute call. The first two rows shows two input argument being read from a HBM bank. The DATA_COPY and SEQUENTIAL access macros allow a data movers (dm_8 and dm_9) to stream this data to the PE mmult which then executes. The mmult then writes to a stream connected to the subsequent PE incr_10, which in turn writes to another stream to the PE incr_20. This PE finally triggers the output data mover streams which eventually write results back to the HBM bank.

Figure 1. HW Event Trace

Profiling in VSC mode can be enabled with these settings,

  1. The accelerator class requires these macros,
    1. PROFILE_KERNEL ("PE function names"): To enable tracing the start and stop of every PE execution
    2. PROFILE_PORT("PE argument names"): To enable profiling of AXI ports for any of the PE arguments
    3. The keyword all can be used for profiling all PEs or all ports.
      Note: Using all on accelerator with many AXI ports (every PE argument and platform port connection) can cause Vivado routing issues, preventing the design from closing timing. Then, it is recommended to created hardware traces on specific ports as required.
    4. Modifying these macros will trigger a full Vitis compile and linking including Vivado place and route.
  2. Hardware traces can be enabled with this setting in the xrt.ini file: