Interfaces - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Two types of data transfer occur from the host machine to and from the kernels on the FPGA. Data pointers are transferred between the host CPU and the accelerator through global memory banks. Scalar data is passed directly from the host to the kernel.

The time it takes to transfer data to/from the kernel can also influence the application architecture with respect to throughput goals. Due to the high overhead for data transfer, it is important to think about overlapping the computation with the communication (data movement) that is present in your application. Refer to Designing Efficient Kernels in the Vitis HLS User Guide (UG1399).

The Vitis HLS tool, which is part of the Vitis core development kit, automatically assigns interface ports for the parameters of your C/C++ kernel function. These port assignments are made during the v++ compilation process. The following sections provide additional details of these interface ports, and your ability to manually assign them, or override the default assignments using the INTERFACE pragma. If there are no user-defined INTERFACE pragmas in the code, then the following interface protocols are assigned by the Vitis tool:

  • AXI4 Master interfaces (m_axi) are assigned to pointer arguments of the C/C++ function.
  • AXI4-Lite interfaces (s_axilite) are assigned to scalar arguments, control signals for arrays, global variables, and the return value of the software function.
  • Vitis HLS automatically infers burst transactions to aggregate memory accesses to maximize the throughput bandwidth and/or minimize the latency. For more information on burst transfers, refer to Optimizing Burst Transfers in the Vitis HLS User Guide (UG1399).
  • When hls::stream is used to define a parameter type, the Vitis HLS tool infers an axis streaming interface.