Interpreting TLM Waveform Data for Third-Party Simulators - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
  1. Under the respective design hierarchy in the waveform windows, for each TLM—TLM socket connection, the following information is visible as waveforms.
    1. For memory mapped AXI4 interfaces, the bus transaction is visible as six channels:
      • <socket_name>: This channel contains statistics such as whether transaction is read/write and a unique mark to differentiate information in sub channels. This also indicates the number of transactions completed.
      • <socket_name>_AW: This channel contains the transaction information of Write Address.
      • <socket_name>_W: This channel contains the transaction information of Write Data.
      • <socket_name>_B: This channel contains the transaction information of the corresponding Write Response.
      • <socket_name>_AR: This channel contains the transaction information of Read Address.
      • <socket_name>_R: This channel contains the transaction information of Read Data.

      Detailed attributes for each channel like burst size, burst type, response, etc. are visible as attributes in each channel.

    2. For AXI4-Stream, the bus transaction is visible in one channel only named after the socket_name. This contains the information like TID, TDEST, TDATA, etc. as attributes.
Note: TLM waveform viewing is only supported for Questa Advanced Simulator and Xcelium. The information on the usage of waveform, adding socket to waveform view, and detailed view of attributes can be referred to its respective third-party simulator user guide.