The HLS Synthesis report is a spreadsheet listing the module hierarchy in the left column. This section is describing one section of the HLS report: Performance and Resource Estimates. Each module and loop generated by the HLS run is represented in this hierarchy. The HLS Synthesis report contains the following columns:
- Issue Type
- Latency in clock cycles
- Latency in absolute time (ns)
- Iteration Latency
- Trip Count
- Utilization Estimates of BRAM, DSP, FF, and LUT
If this information is part of a hierarchical block, it will sum up the information of the blocks contained in the hierarchy. Therefore, the hierarchy can also be navigated from within the report when it is clear which instance contributes to the overall design.