Manually Creating Sources for Mirror Modules - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
  1. For all ipc_axis_<master/slave> IP modules instantiated in the Vitis platform project, a similar mirror IP module is created.
  2. The example source code for these mirror modules is available at https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/emulation/external_traffic_generator/example.
    1. ipc_axis_master_mirror: Example source code for the mirror module to the ipc_axis_master IP initiated in the Vitis platform:
      • sim_ipc_axis_master_mirror.h
      • sim_ipc_axis_master_mirror.cpp
      • sim_ipc_axis_master_mirror.sv
    2. ipc_axis_slave_mirror: Example source code for the mirror module to the ipc_axis_slave IP initiated in the Vitis platform:
      • sim_ipc_axis_slave_mirror.h
      • sim_ipc_axis_slave_mirror.cpp
      • sim_ipc_axis_slave_mirror.sv
    3. utils: This directory contains the utility file required by the mirror modules:
      • sim_ipc_axis_master.h
      • sim_ipc_axis_master.cpp
      • sim_ipc_axis_slave.h
      • sim_ipc_axis_slave.cpp
    4. run.sh: This file is the example compilation, elaboration, and script for the mirror modules.
  3. Each mirror module has a stub system Verilog module, which you need to instantiate in the Traffic Generator top where a signal connection is being made. This module provides a pin level bus interface for the AXI4-Stream bus protocol. This bus interface connects to the corresponding SV interface or Traffic Generator RTL module interface driving the AXI4-Stream traffic. This stub SV module is a placeholder for the implementation of the SystemC module. The SystemC module has a transactor which converts the pin level signaling to a axis_payload (TLM payload). This payload is then serialized using google protobuf and sent through socket communication to the Vitis emulation process. In the Vitis emulation process, for the ipc_axis_<master/slave> IP, this payload is de-serialized, converted to pin level, and driven to the bus interface of User kernel.
  4. The SystemC model uses various libraries underneath to function. All the library binaries and headers are available in Vivado as part of the installation. The example run.sh script contains the path to all these libraries and headers.
  5. Use the above information about mirror module sources as an example to develop your own mirror modules.
  6. You can write a compilation, elaboration, and simulation script taking hints from the provided script (run.sh).