Memory Interface Width Considerations - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The maximum data width from the global memory to and from the kernel is 512 bits. To maximize the data transfer rate, it is recommended that you use this full data width. By default in the Vitis kernel flow, the Vitis HLS tool automatically re-sizes the kernel interface ports up to 512 bits to improve burst access. For more information, refer to Automatic Port Width Resizing in the Vitis HLS User Guide (UG1399).

Tip: The Synthesis Summary report in Vitis HLS includes information about port widening. However, to review this report you will need to launch the tool.

There are some pros and cons to using the automatic port width resizing feature which you should consider when using this feature:

  • Improves the read latency from memory as the tool is reading a big vector, instead of the data type size.
  • Adds resources as it needs to buffer the big vector, and shift the data to the data path size.
  • Automatic port width resizing supports only standard C data types and does not support non-aggregate types such as ap_int, ap_uint, struct, or array.
Tip: You can disable automatic port widening, and manually size the kernel port if needed.