The Vivado kernel project is configured to run synthesis and implementation in out-of-context (OOC) mode. A Xilinx Design Constraints (XDC) file is populated in the design to provide default clock frequencies for this purpose.
You should always synthesize the RTL kernel before packaging it with the
package_xo command. Running synthesis is useful to determine
whether the kernel synthesizes without errors. It also provides estimates of resource
utilization and operating frequency. Without pre-synthesizing the RTL kernel you could
encounter errors during the
v++ linking process, and it could be much
harder to debug the cause.
To run OOC synthesis, click Run Synthesis from the menu.
The synthesized outputs can also be used to package the RTL kernel with a netlist source, instead of RTL source.