Pipeline Execution - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

If a kernel can accept more data while it is still operating on data from previous transactions, XRT can send the next batch of data as described in Temporal Data Parallelism: Host-to-Kernel Dataflow. Pipeline mode lets the kernel overlap multiple kernel runs, which improves the overall throughput.

To support pipeline mode the kernel has to use the ap_ctrl_chain protocol which is the default protocol used by Vitis HLS. This protocol can also be enabled by assigning the #pragma HLS INTERFACE to the function return as shown in the following example.

void kernel_name( int *inputs,
                  ...         )// Other input or Output ports
{
#pragma HLS INTERFACE ap_ctrl_chain port=return bundle=control

For pipeline execution to be successful, the kernel should have a longer latency for the queue of the kernel, or else there might be insufficient time for the kernel to process each batch of data, and you would not see the benefit of the pipeline. If a pipelined kernel is unable to process data in a pipelined manner, it reverts to sequential execution.

Important: To take advantage of the host-to-kernel dataflow, the kernel must also be written to process data in stages, such as pipelined at the loop-level, as discussed in Loop Pipelining, or pipelined at the task-level, as discussed in Dataflow Optimization.

For legacy reasons, XRT-managed kernels also support pure sequential mode that can be configured using the ap_ctrl_hs block protocol for the function return in the #pragma HLS INTERFACE.