Platform and System Diagrams - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The Platform and System Diagrams display a representation of the platform resources, and the kernel code integrated onto the platform. They can be viewed in the Vitis™ analyzer from the Link Summary, the Run Summary, or the .xclbin for a project.

The Platform Diagram is a block diagram of the target platform, before the .xclbin is loaded. This diagram shows all DDR banks and PLRAM available, and their available connections. A table at the bottom displays details of bank names with types of memories, their sizes and which SLR region these are available.

The System Diagram shows memory banks or PLRAMs used by the .xclbin. You can also see how the function arguments of Compute Units are connected to AXI4 interfaces. A table at the bottom of the System Diagram displays information for each Compute Unit, Kernels, and Memories. For designs that include AI Engine kernels, the System Diagram also displays information related to those kernels. Features of the System Diagram include the following:

  • Name of the kernel with an indication which SLR this is available.
  • LUT%
  • Register %
  • BRAM % used
  • URAM % used
  • DSP % used
Figure 1. System Diagram with Profile Data

When Run Summary is loaded, the System Diagram includes profile data from the run. The Vitis analyzer automatically runs vp_analyze when the generated xrt.run_summary file has any of the profiling files available. The profile data is added to the table at the bottom of the System Diagram and can also be displayed in the diagram, as shown in the figure above.

The resource information from the table can also be displayed in a box next to each kernel or CU in the System Diagram. The Settings command () lets you display or hide Unused Memory, Interface Ports, Profile Info, and Resource info.

Figure 2. Show Port Info

The ports on a Compute Unit can display the transfer rates on the system diagram, as well as CU Utilization percentage. CU port transfer rates are taken from the Kernel Transfer section of the Profile Summary report. CU utilization statistics are taken from the Compute Unit Utilization section of Profile Summary. The performance data is available as long as Profiling was enabled for Hardware and Hardware Emulation run, using the Vitis compiler --profile option as described in --profile Options.

Device Map

Vitis™ analyzer also provides a Device Map with the Link Summary for a project which can be opened from the Report Navigator pane. The Device Map shows an abstract view of the static and dynamic regions of the target platform, and shows the placement of kernels on the device and the SLRs. You can also see where each Compute Unit is placed inside the dynamic region.

The table at the bottom of the Device Map shows information similar to the table in System Diagram. You can select the rows in this table and the corresponding section is highlighted in the Device Map. The highlight color for any of the objects in the table can be changed by right-clicking the object in the table and selecting the Highlight color. This updated color is used to highlight the selected object on the Device Map. Additionally, the Device Map and System Diagram object support highlighting across multiple views. For example, you can also select the object in the System Diagram or Device Map table, both views highlight the object selected from the table.