RTL Type Kernel Project - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The RTL type kernel delivers a top-level Verilog design consisting of control register and the Vadd sub-modules example design. The following figure illustrates the top-level design configured with two AXI4-master interfaces. Care should be taken if the Control Register module is modified to ensure that it still aligns with the kernel.xml file located in the imports directory of the Vivado kernel project. The example block can be replaced with your custom logic or used as a starting point for your design.

Figure 1. Kernel Type RTL Top

The Vadd example block, shown in the following figure, consists of a simple adder function, an AXI4 read master, and an AXI4 write master. Each defined AXI4 interface has independent example adder code. The first associated argument of each interface is used as the data pointer for the example. Each example reads 16 KB of data, performs a 32-bit add one operation, and then writes out 16 KB of data back in place (the read and write address are the same).

Figure 2. Kernel Type RTL Example

The following table describes some important files in the example IP project, relative to the root of the Vivado project for the kernel, where <kernel_name> is the name of the kernel you specified in the RTL Kernel wizard.

Table 1. RTL Kernel Wizard Source and Test Bench File
Filename Description Delivered with Kernel Type
<kernel_name>_ex.xpr Vivado project file All
imports directory
<kernel_name>.v Kernel top-level module All
<kernel_name>_control_s_axi.v RTL control register module RTL
<kernel_name>_example.sv RTL example block RTL
<kernel_name>_example_vadd.sv RTL example AXI4 vector add block RTL
<kernel_name>_example_axi_read_master.sv RTL example AXI4 read master RTL
<kernel_name>_example_axi_write_master.sv RTL example AXI4 write master RTL
<kernel_name>_example_adder.sv RTL example AXI4-Stream adder block RTL
<kernel_name>_example_counter.sv RTL example counter RTL
<kernel_name>_exdes_tb_basic.sv Simulation test bench All
<kernel_name>_cmodel.cpp Software C-Model example for software emulation. All
<kernel_name>_ooc.xdc Out-of-context Xilinx constraints file All
<kernel_name>_user.xdc Xilinx constraints file for kernel user constraints. All
kernel.xml Kernel description file All
package_kernel.tcl Kernel packaging script proc definitions All
post_synth_impl.tcl Tcl post-implementation file All
exports directory
src/host_example.cpp Host code example All
makefile Makefile example All