Random Access and the RAMA IP - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
English (United States)
Release Date
2021.2 English

HBM performs well in applications where sequential data access is required. However, for applications requiring random data access, performance can vary significantly depending on the application requirements (for example, the ratio of read and write operations, minimum transaction size, and size of the memory space being addressed). In these cases, the addition of the Random Access Memory Attachment (RAMA) IP to the target platform can significantly improve random memory access efficiency in cases where the required memory exceeds the 256 MB limit of a single HBM PC. Refer to RAMA LogiCORE IP Product Guide (PG310) for more information.

Tip: To effectively use the RAMA IP in your application the kernel should access memory from multiple HBM PCs and should use a static single ID on the AXI transaction ID ports (AxID), or slowly changing (pseudo-static) AXI transaction IDs. If these conditions are not met, the thread creation used in the RAMA IP to improve performance has little effect, and consumes programmable logic resources for no purpose.

Add the RAMA IP to the target platform during the system linking process using the following v++ command option to specify a Tcl script to define the ports of interest:

v++ -l --advanced.param compiler.userPreSysLinkOverlayTcl=<path_to>/user_tcl_file.tcl
Within this user-specified Tcl script, an API is provided to let you configure the HMSS resource:
hbm_memory_subsystem::ra_master_interface <Endpoint AXI master interface> [get_bd_cells hmss_0]

The following example has two AXI master ports (M00_AXI and M01_AXI) for random access:

hbm_memory_subsystem::ra_master_interface [get_bd_intf_pins dummy/M00_AXI] [get_bd_cells hmss_0]
hbm_memory_subsystem::ra_master_interface [get_bd_intf_pins dummy/M01_AXI] [get_bd_cells hmss_0]
validate_bd_design -force

It is important to end the Tcl script with the validate_bd_design command as shown above to allow the information to be collected correctly by the HBM subsystem, and the block design to be updated.