Revision History - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Getting Started with Vitis Revision History

The following table shows the revision history for Getting Started with Vitis.
Section Revision Summary
12/15/2021 Version 2021.2
N/A No changes to this section.
10/22/2021 Version 2021.2
Changed Behavior Updated table.
Setting Up the Environment to Run the Vitis Software Platform Updated to latest version.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
Installation Requirements Updated to 2021.1.
Installing the Vitis Software Platform Updated to 2021.1.
Setting Up the Environment to Run the Vitis Software Platform Updated to 2021.1.
Data Center Application Acceleration Development Flow Updated Running the Application description and figure.
Embedded Processor Application Acceleration Development Flow Updated Running the Application description and figure.
Methodology for Developing C/C++ Kernels Added description and link to UG1399.
About the High-Level Synthesis Compiler Updated link to UG1399.

Developing Applications Revision History

The following table shows the revision history for Developing Applications.
Section Revision Summary
12/15/2021 Version 2021.2
Host Programming Added GCC version description.
Adding C-Models to RTL Kernels Added note on user-managed kernels.
10/22/2021 Version 2021.2
Device Topology Minor file clean up.
Kernel Properties Updated tip note.
Non-Software Controlled Kernels Updated cross-references.
Streaming Interfaces Updated section.
RTL Kernels Added C-Model description.
Packaging the RTL Code as a Vitis XO Added C-Model description.
Adding C-Models to RTL Kernels Added section.
Auto-Restarting Kernels Added section.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
Programming Model Updated section.
Device Topology Updated description to CPU.
Kernel Properties Updated section.
Clock and Reset Requirements Updated table.
Command Queues Added note.
Host Programming Added section.
C/C++ Kernels Updated link.
Process Execution Modes Updated section.
Interfaces Added throughput and link.
Dataflow Optimization Added best practice and link.
Working with Auto-Restarting Kernels Added with subtopics.
Kernel Interface Requirements Updated section.
RTL Kernels Updated section.
Creating User-Managed RTL Kernels Added with subtopics.

Building and Running the Application Revision History

The following table shows the revision history for Building and Running the Application.
Section Revision Summary
12/15/2021 Version 2021.2
Compiling and Linking for x86 Added OpenCL description.
Compiling and Linking for Arm Added OpenCL description.
Running Multiple Implementation Strategies for Timing Closure Updated strategies description in note.
Running Emulation on Data Center Accelerator Cards Updated emconfig description in #2.
10/22/2021 Version 2021.2
Compiling and Linking for x86 Added important on programming versions.
Compiling and Linking for Arm Added important on programming versions.
HBM Configuration and Use Updated HBM memory and segments.
Specifying Streaming Connections between Compute Units Added important note on --connectivity.sc error.
Running Multiple Implementation Strategies for Timing Closure Added important note on running all implementations.
Using -to_step and Launching Vivado Interactively Added note on project.bit information.
Xilinx TLM – SystemC Library for ESL Modelling Added section.
Using I/O Traffic Generators Added software emulation updates.
Adding Traffic Generators to Your Design Added hardware and software emulation description.
AXI4-Stream I/O Model for Streaming Traffic Added software emulation updates.
Writing Traffic Generators in SV/Verilog Added section.
Running Traffic Generators Added notes about emulation terminals.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
Building the Device Binary Updated to Vivado IP packager.
Compiling Kernels with Vitis HLS Updated description.
Assigning Compute Units to SLRs Added important note.
Managing Clock Frequencies Updated section.
Running Multiple Implementation Strategies for Timing Closure Minor update.
Output Directories of the v++ Command Updated profile_summary.csv and timeline_trace.csv
Running Emulation on an Embedded Processor Platform Updated profile_summary.csv and timeline_trace.csv
Working with SystemC Models Added.

Profiling, Optimizing, and Debugging the Application Revision History

The following table shows the revision history for Profiling, Optimizing, and Debugging the Application.
Section Revision Summary
12/15/2021 Version 2021.2
N/A No changes to this section.
10/22/2021 Version 2021.2
Enabling Profiling in Your Application Added tip note in Host Application XRT Native API description and Power Profile.
Enabling No Overhead Profiling Added section.
Interpreting the HLS Report Updated column titles.
Profile Summary Report Updated section.
Generating and Opening the Profile Summary Report Updated section.
Generating and Opening the Waveform Reports Added step 5.
Interpreting TLM Waveform Data for Third-Party Simulators Added section.
Command Line Debug Flow Added two debug flows description.
Software Emulation Debug for Embedded Processors Added section.
Software Emulation Debug for Alveo Accelerators Added section.
Launching Host and Kernel Debug Added listener port description.
07/19/2021 Version 2021.1
Enabling Kernels for Debugging with Chipscope Added Important and Tip notes and flattened design description in System ILA.
06/16/2021 Version 2021.1
Enabling Profiling in Your Application Updated power_profile.
Continuous Trace Capture Added.
Custom Profiling of the Host Application Updated section.
Profiling of C++ Code Updated user_range code and removed note.
Generating and Opening the Profile Summary Report Updated #2 code and profile_summary.
Timeline Trace Updated title and description.
Generating and Opening the Timeline Trace Updated title and description.
Interpreting the Timeline Trace Updated title and description.
Generating and Opening the Waveform Reports Updated #2 code.
Interpreting Data in the Waveform Views Updated description.
Multiple In-Order Command Queues Added note.
GDB-Based Debugging Removed hardware.
GDB Kernel-Based Debugging Removed hardware.
Launching Host and Kernel Debug Removed hardware.
Debugging in Hardware Emulation Updated figure.
GDB-Based Debugging in Hardware Emulation Removed section.
Enable Waveform Debugging with the Vitis Compiler Command Updated #2 code.
Using the Xilinx xbutil Utility Updated Performance Monitor descriptions.
Kernel Hangs Due to AXI Violations Updated #4 tip note.
Example of Command Line Debugging Updated #8.

Vitis Environment Reference Materials Revision History

The following table shows the revision history for Vitis Environment Reference Materials.
Section Revision Summary
12/15/2021 Version 2021.2
Vitis Compiler Command Updated description.
--package Options Added default descriptions.
emconfigutil Utility Updated emconfig description in note.
launch_emulator Utility Updated -kernel-dbg.
10/22/2021 Version 2021.2
Vitis Compiler General Options Updated --trace_memory.
--connectivity Options Added important note on --connectivity.sc error.
--profile Options Updated note, profile code block, and added --profile.memory:<arg>.
--vivado Options Updated --vivado.prop code in important note.
Vitis Compiler Configuration File Added tip note on compilation and linking.
launch_emulator Utility Updated launch_emulator.py Utility Options table.
xbutil Utility Updated link and codeblock.
xbmgmt Utility Updated link and codeblock.
xrt.ini File Updated table.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
Vitis Compiler General Options Updated descriptions.
--advanced Options Removed gdb option in table and updated --advanced.param table.
--clock Options Updated section.
--connectivity Options Added --connectivity.connect and re-organized.
--hls Options Added --hls.export_mode.
--package Options Added tip note in --package.boot_mode and updated --package.ps_elf.
Vitis Compiler Configuration File Updated table.
launch_emulator Utility Updated section.
package_xo Command Updated -kernel_files description.
RTL Kernel XML File Updated hwControlProtocol description.
xbutil Utility Added script description.
xbmgmt Utility Added Tip note.
xclbinutil Utility Updated table.
xrt.ini File Updated Debug and Emulation tables.

Using the Vitis Analyzer Revision History

The following table shows the revision history for Using the Vitis Analyzer.
Section Revision Summary
12/15/2021 Version 2021.2
N/A No changes to this section.
10/22/2021 Version 2021.2
Using the Vitis Analyzer Added Device Map to Link Summary bullet.
Working with Reports Updated figure and description.
Configuring the Vitis Analyzer Updated figure.
Compare Two Timeline Trace Reports Updated figure and title.
Using the Floating Ruler Added section.
Platform and System Diagrams Updated vp_analyze description.
AI Engine Graphs and Arrays Added note about more views.
Creating an Archive File Removed HLS synthesis report.
Using the Floating Ruler Added section.
07/19/2021 Version 2021.1
Adding Hardware Interfaces Added important note to General Requirements.
Enabling Hardware Emulation for Extensible XSA Added important note to #3.
Validating an Embedded Platform Added.
06/16/2021 Version 2021.1
Configuring the Vitis Analyzer Updated Run Summary.
Compare Two Timeline Trace Reports Updated figure.
Platform and System Diagrams Updated profile_summary.csv and added Device Map.
Link Summary: Multiple Strategies and Timing Reports Added.
Creating an Archive File Updated profile_summary.csv, timeline_trace.csv, and note.

Using the Vitis IDE Revision History

The following table shows the revision history for Using the Vitis IDE.
Section Revision Summary
12/15/2021 Version 2021.2
N/A No changes to this section.
10/22/2021 Version 2021.2
Building the System Added tip note and Cancel Build figure.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
Output Directories from the Vitis IDE Updated profile_summary.csv and timeline_trace.csv
vitis -debug Command Line Updated -kernels.
Vitis Binary Container Settings Updated figure and description.
Vitis IDE Debug Flow Removed hardware and note at the end.

Using Vitis Embedded Platforms Revision History

The following table shows the revision history for Using Vitis Embedded Platforms.
Section Revision Summary
12/15/2021 Version 2021.2
Packaging Images Updated stages description.
Packaging Images with Ext4 rootfs in the Vitis IDE Updated to 2021.2.
Adding Hardware Interfaces Updated descriptions and added figures.
Special Considerations for Embedded Platform Creation Added platform recommendations.
10/22/2021 Version 2021.2
Software Package Management in PetaLinux rootfs Updated DNF package manager description.
Testing Your Platform Updated XRT basic test description.
Run Baremetal Software Emulation Updated platform verification description.
07/19/2021 Version 2021.1
Platform Types Minor updates.
06/16/2021 Version 2021.1
Platform Types Minor updates.
Enabling Hardware Emulation for Extensible XSA Updated 2b and 2c.

Additional Information

The following table shows the revision history for Additional Information.
Section Revision Summary
12/15/2021 Version 2021.2
N/A No changes to this section.
10/22/2021 Version 2021.2
xbutil Utility - Legacy Updated tip note.
xbmgmt Utility - Legacy Updated tip note.
Streaming Data Transfer between Kernels Removed section.
Free-Running Kernel Updated section.
07/19/2021 Version 2021.1
N/A No changes to this section.
06/16/2021 Version 2021.1
OpenCL Programming Added.
Understanding an FPGA Architecture Minor updates.
Legacy Reference Added.
Coding Guidelines for Free-Running Kernels Added Tip note.