Running XVC and HW Servers - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
The following steps are required to run the Xilinx virtual cable (XVC) and HW servers, host applications, and also trigger and arm the debug cores in the Vivado hardware manager.
  1. Add debug IP to the kernel as discussed in Enabling Kernels for Debugging with Chipscope.
  2. Modify the host program to pause at the appropriate point as described in Enabling ILA Triggers for Hardware Debug.
  3. Set up the environment for hardware debug, using an automated script described in Automated Setup for Hardware Debug, or manually as described in Manual Setup for Hardware Debug.
  4. Run the hardware debug flow using the following process:
    1. Launch the required XVC and the hw_server of the Vivado hardware manager.
    2. Run the host program and pause at the appropriate point to enable setup of the ILA triggers.
    3. Open the Vivado hardware manager and connect to the XVC server.
    4. Set up ILA trigger conditions for the design.
    5. Continue execution of the host program.
    6. Inspect kernel activity in the Vivado hardware manager.
    7. Rerun iteratively from step b (above) as required.