Profiling also shows a timeline trace for various phases of run in the application layer, as shown in the picture. This is presented under the "SystemCompile" tab in Vitis Analyzer. These timeline trace rows are explained below.
- Send body: each box captures the start and end of a send iteration, including the execution of any user-written code in the send lambda function.
- Receive body: each box captures the start and end of a receive iteration, including any user-written code. In this example, the receive iteration is very fast (tiny in the picture) compared to that of send.
- Compute: each box captures the start of a compute call until the application receives a result (a get() on the C++ future).
- Input transfers: these are input data transfers for each compute job. In this example, they are writes to the HBM memory bank.
- CU-pipeline: the application layer maintains multiple software job pipelines, typically more than the number of CUs in the hardware, for efficient execution. Each row is a separate software pipeline, and it captures every job execution from the start of submission in this pipeline until the completion of the job by the hardware.
- Detail: this row captures some key events in the execution model, primarily the issuance of the start signal and receiving the done for each compute call.
- Output transfers: these are output data transfers for each compute job. In this example, they are data reads from the HBM memory bank.
Figure 1. Timeline Trace