Timing Closure Considerations - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Design performance and timing closure can vary when moving across Vitis releases or target platform(s), especially when one of the following conditions is true:

  • Floorplan constraints were needed to close timing.
  • Device or SLR resource utilization was higher than the typical guideline:
    • LUT utilization was higher than 70%
    • DSP, RAMB, and UltraRAM utilization was higher than 80%
    • FD utilization was higher than 50%
  • High effort compilation strategies were needed to close timing.
The utilization guidelines provide a threshold above which the compilation of the design can take longer, or performance can be lower than initially estimated. For larger designs which usually require using more than one SLR, specify the kernel/DDR association with the v++ --config option, as described in Mapping Kernel Ports to Memory, while verifying that any floorplan constraint ensures the following:
  • The utilization of each SLR is below the recommended guidelines.
  • The utilization is balanced across SLRs if one type of hardware resource needs to be higher than the guideline.

For designs with overall high utilization, increasing the amount of pipelining in the kernels, at the cost of higher latency, can greatly help timing closure and achieving higher performance.

For quickly reviewing all aspects listed above, use the fail-fast reports generated throughout the Vitis application acceleration development flow using the -R option as described below (refer to Controlling Report Generation for more information):

  • v++ –R 1
    • report_failfast is run at the end of each kernel synthesis step
    • report_failfast is run after opt_design on the entire design
    • opt_design DCP is saved
  • v++ –R 2
    • Same reports as with -R 1, plus:
    • report_failfast is post-placement for each SLR
    • Additional reports and intermediate DCPs are generated

All reports and DCPs can be found in the implementation directory, including kernel synthesis reports:

<runDir>/_x/link/vivado/prj/prj.runs/impl_1

For more information about timing closure and the fail-fast report, see the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).