Often the hardware design comprising the platform hardware is co-developed with Vitis AI Engine graphs and PL kernels, possibly by different teams. The Vitis Export flow enables bi-directional hardware hand-offs between the Vivado Design Suite and the Vitis tools to enable these design teams to work with loose coupling, sharing system design updates at convenient check points rather than with every iteration.
The Vitis Export flow enabled by v++ --link --export_archive performs standard linking
design modifications, but stops before running Vivado synthesis and instead encapsulates all relevant design data (BD, IP repository) and
XCLBIN metadata for the Xilinx Runtime (XRT) into a Vitis Metadata Archive (.vma) file,
forgoing the normal automated Vivado simulation,
synthesis and implementation runs.
At the design level, the v++ command
operates entirely within a dynamic region block design container
(BDC) in the extensible hardware platform. Based on source input files, the v++ linker instantiates user-defined PL kernels,
configures platform IP such as AI Engine, NoC, and soft interconnects, adds required design IP
for AXI buses, clock domain crossing, data width conversion, and FIFO buffering, adds
networks for hardware debugging, trace, and clocking, and creates connections between IP
within the dynamic region.
The .vma file is imported into the
original extensible platform project in the Vivado Design Suite using the vitis::import_archive Tcl procedure. The .vma IP repository is added to the Vivado project's IP repository and a new active variant for the dynamic
region BDC is created. Development can then continue in the Vivado project, including additional design modifications, simulation,
synthesis, and implementation.
The Vitis Export flow is mainly used to make
modifications to the platform in Vivado after
importing the .vma file. After implementation and
timing closure, the write_hw_platform -fixed command
has been enhanced to encapsulate the XRT metadata from the .vma file into the output .xsa.
You can also export the XSA for the hardware emulation target from the Vivado tool and run emulation in the Vitis tool.
The flow described here can be repeated through any number of design
iterations. The platform .xsa file can be exported
from Vivado and passed back to the Vitis tools. The updated system design .vma file produced by the v++
--link --export_archive command can be re-imported into the Vivado tools. The flow supports testing the design on
hardware and hardware emulation.