Working with SystemC Models - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

SystemC models in the Vitis application acceleration development flow allow you to quickly model an RTL algorithm for rapid analysis in software and hardware emulation. Using this approach you can model portions of your system while the RTL kernel is still in development, but you want to move forward with some system analysis.

The SystemC model feature supports all the XRT-managed kernel execution models using ap_ctrl_hs and ap_ctrl_chain. It also supports modeling both AXI4 memory mapped interfaces (m_axi) and AXI4-Stream interfaces (axis), as well as register reads and write of the s_axilite interface.

You can model your kernel code in SystemC TLM models, provide interfaces to other kernels and the host application, and use it during emulation. You can create a Xilinx object file (XO) to link the SystemC model to other kernels in your xclbin. The sections that follow discuss the creation of SystemC models, the use of the create_sc_xo command to create the XO, and generating the xclbin using the v++ command.

Tip: Keep in mind that the SystemC model is not cycle accurate, and therefore impacts the timing results of your emulation. It does not reflect the true bandwidth, latency, or throughput of the RTL code.