Generate traffic using the existing test bench written in the System Verilog/Verilog with slight modification to your test bench hierarchy, as explained below.
As shown in the figure above, the external test bench (on the left) and the Vitis emulation (on the right), both run as separate simulation processes. To establish communication between two processes using IPC, you must instantiate SIM_IPC Master/Slave modules.
Perform the following modifications:
- Add IPC modules in the Vitis
emulation design. These are available as prepackaged XOs, and you can insert them
v++command line as described in AXI4-Stream I/O Model for Streaming Traffic.
- Add SIM IPC modules in your SV/V test bench. Instantiate the
ipc_axis_master_mirrormodule inside the Traffic Generator top and make the pin level connection via an SV interface. The
ipc_axis_master_mirrorconverts the pin level AXI transactions to
generic_payloadand sends through the IPC sockets to the
ipc_axis_mastermodule in the Vitis emulation design. Similarly, there is an
ipc_axis_slave_mirrormodule that is instantiated in the Traffic Generator top to connect to the
ipc_axis_slavemodule in the Vitis emulation design.
The same technique can be deployed to drive traffic from the external System Verilog/Verilog traffic generators/test benches to the AI Engine simulator or x86-simulator.
ipc_axis_master_mirroris the same
ipc_ais_slave_mirroris the same
- Collectively, these are xtlm_ipc_verilog_stub modules. All names are interchangeable.