Writing Traffic Generators in SV/Verilog - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

You can also generate traffic using the existing test bench written in System Verilog/Verilog with slight modification to your test bench hierarchy as explained below.

Figure 1. Test Bench Hierarchy

As shown in the figure above, the external test bench (on the left) and the Vitis emulation (on the right), both run as separate simulation processes. You need to instantiate SIM_IPC Master/Slave modules to establish communication between two processes using IPC.

Perform the following modifications:

  1. Add IPC modules in the Vitis emulation design. These are available as prepackaged XOs and you can insert them using the v++ command line as described in AXI4-Stream I/O Model for Streaming Traffic.
  2. Add SIM IPC modules in your SV/V test bench. Instantiate the ipc_axis_master_mirror module inside the Traffic Generator top and make the pin level connection via an SV interface. The ipc_axis_master_mirror converts the pin level AXI transactions to generic_payload and sends through the IPC sockets to the ipc_axis_master module in the Vitis emulation design. Similarly, there is an ipc_axis_slave_mirror module that is instantiated in the Traffic Generator top to connect to the ipc_axis_slave module in the Vitis emulation design.