dmatest - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
Important: This option cannot be used with embedded processor platforms.

The dmatest command is used to validate the card memory throughput by performing data transfer tests between the host machine and global memory on a specified card. The dmatest is run as part of the validate command.

It has the following command line format:

xbutil dmatest [-d card] [-b [0x]block_size_KB]

The following table lists the available options.

Table 1. xbutil dmatest Command Options
Option Description Required
-d <card> Specifies the target card. <card> can be specified as either the card_id or Bus:Device:Function (BDF). Defaults to card_id = 0 if not specified.
Note: Use the xbutil scan command to display both the card_id and BDF for installed cards.
N
-b blocksize Specifies the test block size (in KB). Block size defaults to 65536 (KB) if -b option is not specified. Block size must be a power of 2.

The block size can be specified in both decimal or hexadecimal formats. For example, both -b 1024 and -b 0x400 set the block size to 1024 KB.

N

It is necessary to program the xclbin prior to running dmatest. See program to program the xclbin.

The dmatest command only performs throughput tests on those DDR banks or HBM pseudo-channels (PCs) accessed by the xclbin programmed to the card.

An example of the command output on a U200 with an xclbin using DDR banks 0, 1, 2, and 3 is shown below:

INFO: Found total 1 card(s), 1 are usable
Total DDR size: 65536 MB
Reporting from mem_topology:
Data Validity & DMA Test on bank0
Host -> PCIe -> FPGA write bandwidth = 11341.5 MB/s
Host <- PCIe <- FPGA read bandwidth = 11097.3 MB/s
Data Validity & DMA Test on bank1
Host -> PCIe -> FPGA write bandwidth = 11414.6 MB/s
Host <- PCIe <- FPGA read bandwidth = 10981.7 MB/s
Data Validity & DMA Test on bank2
Host -> PCIe -> FPGA write bandwidth = 11345.1 MB/s
Host <- PCIe <- FPGA read bandwidth = 11189.2 MB/s
Data Validity & DMA Test on bank3
Host -> PCIe -> FPGA write bandwidth = 11121.7 MB/s
Host <- PCIe <- FPGA read bandwidth = 11375.7 MB/s
INFO: xbutil dmatest succeeded.

Similarly, an example of the command output on a U50 with an xclbin using HBM port 0, 1, 2, and 3 is shown below:

INFO: Found total 1 card(s), 1 are usable
Total DDR size: 0 MB
Reporting from mem_topology:
Data Validity & DMA Test on HBM[0]
Buffer Size: 256 MB
Host -> PCIe -> FPGA write bandwidth = 11950.9 MB/s
Host <- PCIe <- FPGA read bandwidth = 11940.3 MB/s
Data Validity & DMA Test on HBM[1]
Buffer Size: 256 MB
Host -> PCIe -> FPGA write bandwidth = 11947 MB/s
Host <- PCIe <- FPGA read bandwidth = 11958.1 MB/s
Data Validity & DMA Test on HBM[2]
Buffer Size: 256 MB
Host -> PCIe -> FPGA write bandwidth = 12077.2 MB/s
Host <- PCIe <- FPGA read bandwidth = 12064.1 MB/s
Data Validity & DMA Test on HBM[3]
Buffer Size: 256 MB
Host -> PCIe -> FPGA write bandwidth = 11989.5 MB/s
Host <- PCIe <- FPGA read bandwidth = 11976 MB/s
INFO: xbutil dmatest succeeded.

If no xclbin is programmed, a message similar to the following will be displayed.

INFO: Found total 1 card(s), 1 are usable
'uuid' invalid, please re-program xclbin.