AXI4-Lite Interface - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Overview

An HLS IP or kernel can be controlled by a host application, or embedded processor using the Slave AXI4-Lite interface (s_axilite) which acts as a system bus for communication between the processor and the kernel. Using the s_axilite interface the host or an embedded processor can start and stop the kernel, and read or write data to it. When Vitis HLS synthesizes the design the s_axilite interface is implemented as an adapter that captures the data that was communicated from the host in registers on the adapter. Refer to Vitis-HLS-Introductory-Examples/Interface/Register on Github for examples of some of these concepts.

The AXI4-Lite interface performs several functions within a Vivado IP or Vitis kernel:

  • It maps a block-level control mechanism which can be used to start and stop the kernel.
  • It provides a channel for passing scalar arguments, pointers to scalar values, function return values, and address offsets for m_axi interfaces from the host to the IP or kernel
  • For the Vitis Kernel flow:
    • The tool will automatically infer the s_axilite interface pragma to provide offsets to pointer arguments assigned to m_axi interfaces, scalar values, and function return type.
    • Vitis HLS lets you read to or write from a pointer to a scalar value when assigned to an s_axilite interface. Pointers are assigned by default to m_axi interfaces, so this requires you to manually assign the pointer to the s_axilite using the INTERFACE pragma or directive:
      int top(int *a, int *b) {
      #pragma HLS interface s_axilite port=a
    • Bundle: Do not specify the bundle option for the s_axilite adapter in the Vitis Kernel flow. The tool will create a single s_axilite interface that will serve for the whole design.
      Important: HLS will return an error if multiple bundles are specified for the Vitis Kernel flow.
    • Offset: The tool will automatically choose the offsets for the interface. Do not specify any offsets in this flow.
  • For the Vivado IP flow:
    • This flow will not use the s_axilite interface by default.
    • To use the s_axilite as a communication channel for scalar arguments, pointers to scalar values, offset to m_axi pointer address, and function return type, you must manually specify the INTERFACE pragma or directive.
    • Bundle: This flow supports multiple s_axilite interfaces, specified by bundle. Refer to S_AXILITE Bundle Rules for more information.
    • Offset: By default the tool will place the arguments in a sequential order starting from 0x10 in the control register map. Refer to S_AXILITE Offset Option for additional details.