Analyzing the Results of Synthesis

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

After synthesis completes, Vitis HLS automatically creates synthesis reports to help you understand and analyze the performance of the implementation. Examples of these reports include the Synthesis Summary report, Schedule Viewer, Function Call Graph, and Dataflow Viewer . You can view these reports from the Flow Navigator in the Vitis HLS IDE.

Schedule Viewer
Shows each operation and control step of the function, and the clock cycle that it executes in.
Dataflow Viewer
Shows the dataflow structure inferred by the tool, inspect the channels (FIFO/PIPO), to let you examine the effect of channel depth on performance
Function Call Graph Viewer
Displays your full design after C Synthesis or C/RTL Co-simulation to show the throughput of the design in terms of latency and II.

In addition to the various graphs and viewers described above, the Vitis HLS tool provides additional views to expand on the information available for analysis of your design.

Module Hierarchy
Shows the resources and latency contribution for each block in the RTL hierarchy It also indicates any II or timing violations. In case of timing violations, the hierarchy window will also show the total negative slack observed in a specific module.
Performance Profile
Shows details on the performance of the block currently selected in the Module Hierarchy view. Performance is measured in terms of latency and the initiation interval, and includes details on whether the block was pipelined or not.
Resource Profile
Shows the resources used at the selected level of hierarchy, and shows the control state of the operations used.
Properties view
Shows the properties of the currently selected control step or operation in the Schedule Viewer.