Arrays on the Interface - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

In the Vivado IP flow Vitis HLS synthesizes arrays into memory elements by default. When you use an array as an argument to the top-level function, Vitis HLS assumes one of the following:

  • Memory is off-chip.

    Vitis HLS synthesizes interface ports to access the memory.

  • Memory is standard block RAM with a latency of 1.

    The data is ready one clock cycle after the address is supplied.

To configure how Vitis HLS creates these ports:

  • Specify the interface as a RAM or FIFO interface using the INTERFACE pragma or directive.
  • Specify the RAM as a single or dual-port RAM using the storage_type option of the INTERFACE pragma or directive.
  • Specify the RAM latency using the latency option of the INTERFACE pragma or directive.
  • Use array optimization directives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigure the structure of the array and therefore, the number of I/O ports.
Tip: Because access to the data is limited through a memory (RAM or FIFO) port, arrays on the interface can create a performance bottleneck. Typically, you can overcome these bottlenecks using directives.
Arrays must be sized when using arrays in synthesizable code. If, for example, the declaration d_i[4] in Array Interfaces is changed to d_i[], Vitis HLS issues a message that the design cannot be synthesized:
@E [SYNCHK-61] array_RAM.c:52: unsupported memory access on variable 'd_i' which is (or contains) an array with unknown size at compile time.