Figure 1. C/RTL Verification Flow
C/RTL co-simulation uses a C test bench, running the
main() function, to automatically verify the RTL design running in
behavioral simulation. The C/RTL verification process consists of three phases:
- The C simulation is executed and the inputs to the top-level function, or the Design-Under-Test (DUT), are saved as “input vectors.”
- The “input vectors” are used in an RTL simulation using the RTL created by Vitis HLS in Vivado simulator, or a supported third-party HDL simulator. The outputs from the RTL, or results of simulation, are saved as “output vectors.”
- The “output vectors” from the RTL simulation are returned to the
main()function of the C test bench to verify the results are correct. The C test bench performs verification of the results, in some cases by comparing to known good results.
The following messages are output by Vitis™ HLS as verification progresses:
While running C simulation:
INFO: [COSIM 212-14] Instrumenting C test bench ... Build using ".../bin/g++" Compiling dct_test.cpp_pre.cpp.tb.cpp Compiling dct_inline.cpp_pre.cpp.tb.cpp Compiling apatb_dct.cpp Generating cosim.tv.exe INFO: [COSIM 212-302] Starting C TB testing ... Test passed !
At this stage, because the C simulation was executed, any messages written by the C test bench will be output to the Console window and log file.
While running RTL simulation:
INFO: [COSIM 212-333] Generating C post check test bench ... INFO: [COSIM 212-12] Generating RTL test bench ... INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. *** INFO: [COSIM 212-323] Starting verilog/vhdl simulation. INFO: [COSIM 212-15] Starting XSIM ...
At this stage, any messages from the RTL simulation are output in console window or log file.
While checking results back in the C test bench:
INFO: [COSIM 212-316] Starting C post checking ... Test passed ! INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
The following are requirements of C/RTL co-simulation:
- The test bench must be self-checking as described in Writing a Test Bench, and return a value of 0 if the test passes or returns a non-zero value if the test fails.
- Any third-party simulators must be available in the search path to be launched by Vitis HLS.
- Interface Synthesis Requirements must be met.
structson the design interface cannot use the optimization directives listed in Unsupported Optimizations for Co-Simulation.
- IP simulation libraries must be compiled for use with third-party simulators as described in Simulating IP Cores.