Basics of High-Level Synthesis - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The Xilinx Vitis HLS tool synthesizes a C or C++ function into RTL code for acceleration in programmable logic. Vitis HLS is tightly integrated with the Vitis core development kit and the application acceleration design flow.

Some benefits of using a high-level synthesis (HLS) design methodology include:

  • Developing and validating algorithms at the C-level for the purpose of designing at an abstract level from the hardware implementation details.
  • Using C-simulation to validate the design, and iterate more quickly than with traditional RTL design.
  • Controlling the C-synthesis process using optimization pragmas to create high-performance implementations.
  • Creating multiple design solutions from the C source code and pragmas to explore the design space, and find an optimal solution.
  • Quickly recompile the C-source to target different platforms and hardware devices.

HLS includes the following stages:

  1. Scheduling determines which operations occur during each clock cycle based on:
    • When an operation’s dependencies have been satisfied or are available.
    • The length of the clock cycle or clock frequency.
    • The time it takes for the operation to complete, as defined by the target device.
    • The available resource allocation.
    • Incorporation of any user-specified optimization directives.
    Tip: More operations can be completed in a single clock cycle for longer clock periods, or if a faster device is targeted, and all operations might complete in one clock cycle. However, for shorter clock periods, or when slower devices are targeted, HLS automatically schedules operations over more clock cycles. Some operations might need to be implemented as multi-cycle resources.
  2. Binding assigns hardware resources to implement each scheduled operation, and maps operators (such as addition, multiplication, and shift) to specific RTL implementations. For example, a mult operation can be implemented in RTL as a combinational or pipelined multiplier.
  3. Control logic extraction creates a finite state machine (FSM) that sequences the operations in the RTL design according to the defined schedule.