The AMD Vitis™
unified IDE and
v++ common command line provide the ability to create an HLS
component using bottom-up design techniques to ensure the component meets design
requirements before integrating it with other elements into a system design. In an
HLS component, the tool synthesizes a C or C++ function into RTL code for
implementation in the programmable logic (PL) region of an AMD Versal™
adaptive SoC, AMD Zynq™
MPSoC, or AMD FPGA device.
An HLS component can be used to develop and export:
- Vivado IP to be integrated into hardware designs using the Vivado Design Suite and the Embedded Software Development flow as described in Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).
- Vitis kernels for use in hetergeneous compute systems and Data Center application acceleration as described in Vitis Application Acceleration User Guide (UG1393).
The following are the steps for the development of the C++ function.
- Architect the C/C++ algorithm based on Design Principles
- Verify the logic of the source code with a C test bench (C-Simulation)
- Analyze the parallelism and performance of the design (Code Analyzer)
- Generate the RTL from the source code (C-Synthesis)
- Verify the generated RTL module with the C test bench and RTL logic simulation (C/RTL Co-Simulation)
- Review and analyze the HLS synthesis reports and co-simulation reports (Analyze)
- Repeat previous steps until performance goals are met
The HLS component implements the design based on the target flow, default tool configuration, configuration commands, and any optimization pragmas or directives you specify for the design. The following sections describe creating and building the HLS component.