C/RTL Co-Simulation in Vitis HLS

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

If you added a C test bench to the project for simulation purposes, you can also use it for C/RTL co-simulation to verify that the RTL is functionally identical to the C source code. Select the Run Cosimulation command from the Flow Navigator to verify the RTL results of synthesis. The Co-simulation Dialog box is opened as shown in the following figure lets you select which type of RTL output to use for verification (Verilog or VHDL) and which HDL simulator to use for the simulation.

Figure 1. Co-Simulation Dialog Box

The dialog box features the following settings:

Simulator
Choose from one of the supported HDL simulators in the Vivado Design Suite. Vivado simulator is the default simulator.
Language
Specify the use of Verilog or VHDL as the output language for simulation.
Setup Only
Create the required simulation files, but do not run the simulation. The simulation executable can be run from a command shell at a later time.
Optimizing Compile
Enable optimization to improve the runtime performance, if possible, at the expense of compilation time.
Input Arguments
Specify any command-line arguments to the C test bench.
Dump Trace
Specifies the level of trace file output written to the sim/Verilog or sim/VHDL directory of the current solution when the simulation executes. Options include:
all
Output all port and signal waveform data being saved to the trace file.
port
Output waveform trace data for the top-level ports only.
none
Do not output trace data.
Random Stall
Applies a randomized stall for each data transmission.
Compiled Library Location
Specifies the directory for the compiled simulation library to use with third-party simulators.
Extra Options for DATAFLOW
Wave Debug
Enables waveform visualization of all processes in the RTL simulation. This option is only supported when using Vivado logic simulator. Enabling this will launch the Simulator GUI to let you examine dataflow activity in the waveforms generated by simulation. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information on that tool.
Disable Deadlock Detection
Disables deadlock detection, and opening the Cosim Deadlock Viewer in co-simulation.
Channel (PIPO/FIFO) Profiling
Enables capturing profile data for display in the Dataflow Viewer.
Dynamic Deadlock Prevention
Prevent deadlocks by enabling automatic FIFO channel size tuning for dataflow profiling during co-simulation.
Tip: You can pre-configure C/RTL Co-Simulation by right-clicking a solution in the Explorer view and selecting the Solutions Settings command to open the Solution Settings dialog box, and editing the Co-simulation settings. The settings are the same as described above, but can be configured prior to running the simulation.

After the C/RTL co-simulation completes, the console displays the following messages to confirm the verification was successful:

INFO: [Common 17-206] Exiting xsim ...
INFO: [COSIM 212-316] Starting C post checking ...
...
Test passed !
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***

Finished C/RTL cosimulation.

Any printf commands in the C test bench, or hls::print statements in the kernel or IP are also echoed to the console during simulation.

As described in Writing a Test Bench, the test bench verifies output from the top-level function for synthesis, and returns zero to the main() function of the test bench if the output is correct. Vitis HLS uses the same return value for both C simulation and C/RTL co-simulation to determine if the results are correct. If the C test bench returns a non-zero value, Vitis HLS reports that the simulation failed.

The Vitis HLS GUI automatically switches to the Analysis perspective after simulation and opens the Cosimulation Report showing the pass or fail status and the measured statistics on latency and II. Any additional reports that are generated, such as the Dataflow report, are also opened in the Analysis perspective.

Figure 2. Cosimulation Report

The Cosimulation Report displays the full design hierarchy, and if Channel (PIPO/FIFO) Profiling is enabled, you will be able to see details of the dataflow regions as well.

Important: II is marked as NA in the Cosimulation Report unless the transaction number in the RTL simulation is greater than 1. If you want to calculate II, you must ensure there are at least two transactions in the RTL simulation as described in Writing a Test Bench.