Clock and Reset Ports - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

If the design takes more than 1 cycle to complete operation, a clock-enable port (ap_ce) can optionally be added to the entire block using the config_interface command, or in the Vitis HLS GUI using the Solution > Solution Settings > General command.

The operation of the reset is described in Controlling the Reset Behavior, and can be modified using the config_rtl command, also available in the Solutions Settings dialog box.