cosim options apply to the C/RTL
Co-Simulation process used to validate the RTL produced by HLS synthesis. This
includes using the C/C++ test bench used earlier in C-simulation and using the RTL
design in behavioral simulation as described in C/RTL Co-Simulation in Vitis HLS in
the Vitis HLS User Guide
Enables optimizing compilation which eliminates debug constructs. The default is false and compilation is done in debug mode to enable debugging. Enabling optimized compilation of the C/C++ test bench and RTL wrapper increases compilation time, but results in better run time performance.
Specifies an argument list for the behavioral test bench. The specified
<arg>will be passed to the
main()function in the C test bench.
Specifies the compiled library directory used during simulation with third-party simulators. The
<arg>is the path name to the compiled library directory. The library must be compiled ahead of time using the
compile_simlibcommand as explained in the Vivado Design Suite Tcl Command Reference Guide (UG835).
Enables the coverage feature during simulation with the VCS simulator.
Disables the binary test vector format in co-simulation.
Disables deadlock detection, and opening the Cosim Deadlock Viewer in co-simulation.
Disables dependency checks when running co-simulation.
This option enables the dataflow channel profiling to track channel sizes during co-simulation. You must enable this feature to capture dataflow data as described in the Dataflow viewer section of the Vitis HLS User Guide (UG1399).
Enables automatic FIFO channel size tuning for dataflow profiling during co-simulation.
m_axiinterfaces for use with
Specifies the location of test vectors generated during hardware emulation to be used as a test bench during co-simulation. The test vectors are generated by the
syn.rtl.cosim_trace_generationcommand as described in RTL Configuration. This argument lets you specify the kernel and instance name of the Vitis kernel in the hardware emulation simulation results to locate the test vectors for the HLS component.
- cosim.ldflags <arg>
Specifies the options passed to the linker for simulation. This option is typically used to pass include path information or library information for the C/C++ test bench.
- cosim.mflags <arg>
Provides for options to be passed to the compiler for C simulation. This is typically used to speed up compilation.
Enable random stalling of top level interfaces during co-simulation.
Specifies either Verilog or VHDL as the language to use for C/RTL co-simulation. The default is Verilog.
When this option is specified, the simulation binary will be created in the cosim directory of the current HLS component, but simulation will not be executed. Simulation can be launched later from the compiled executable. The default is false, and co-simulation is run after setup is complete.
s_axiliteto configure registers which are stable compared with the prior transaction.
Specify the HDL simulator to be used to co-simulate the RTL with the C testbench. The Vivado simulator (xsim) is the default, unless otherwise specified.
Determines the level of waveform trace data to save during C/RTL co-simulation.
nonedoes not save trace data. This is the default.
allresults in all port and signal waveforms being saved to the trace file.
portonly saves waveform traces for the top-level ports.
port_hiersave the trace information for all ports in the design hierarchy.
The trace file is saved in the sim/Verilog or sim/VHDL folder of the component when the simulation executes, depending on the selection used with the
Specifies the JSON stall file to be used during co-simulation. The stall file can be generated using the
Opens the Vivado simulator GUI to view waveforms and simulation results. Enables waveform viewing of all processes in the generated RTL, as in the dataflow and sequential processes. This option is only supported when using Vitis simulator for co-simulation by setting
cosim.tool=xsim. See Viewing Simulation Waveforms for more information.