Creating a New Vitis HLS Project

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

To create a new project, click the Create New Project link on the Welcome page, or select the File > New Project menu command. This opens the New Vitis HLS Project wizard, as shown in the following figure.

Figure 1. New Vitis HLS Project Wizard

Create a new Vitis HLS project using the following steps:

  1. Specify the project name, which is also the name of the directory in which the project files and folders are written.
  2. Specify the location where the project is written.
    Important: The Windows operating system has a 255-character limit for path lengths, which can affect the Vitis tools. To avoid this issue, use the shortest possible names and directory locations when creating projects, or adding new files.
  3. Click Next to proceed to the Add/Remove Design Files page.
    The Add/Remove Design Files page lets you add C/C++ source files to your project, as shown in the following figure:

  4. Click Add Files, and navigate to the location of the source code files to add to your project.

    Do not add header files (with the .h suffix) to the project using the Add Files button, or the add_files Tcl command. Vitis HLS automatically adds the following directories to the compilation search path:

    • Working directory, which contains the Vitis HLS project directory.
    • Any directory that contains C/C++ files that have been added to the project.

    Header files that reside in these directories are automatically included in the project during compilation. However, you can specify other include paths using the Edit CFLAGS function.

  5. Optionally, click New File to create a new source file to add to your project. The File Browser dialog box opens to let you specify the file name and location to store the new file.
    Tip: If you want to write the new file to the directory that will be created for your new project, you must wait to create the new file until after the project has been created.
  6. You can select a file, and click Edit CFLAGS or Edit CSIMFLAGS to open a dialog box letting you add one or more compiler or simulation flags for the selected file.
    The following figure shows example CFLAGS:

    Compiler flags are standard compiler options for gcc or g++. For a complete list of options, refer to http://gcc.gnu.org/onlinedocs/gcc/Option-Summary.html on the GNU Compiler Collection (GCC) website. The following are some example CFLAGS:

    -I/source/header_files
    Provides the search path to associated header files. You can specify absolute or relative paths to files.
    Important: You must specify relative paths in relation to the working directory, not the project directory.
    -DMACRO_1
    Defines macro MACRO_1 during compilation.
    -fnested-functions
    Defines directives required for any design that contains nested functions.
    Tip: You can use $::env(MY_ENV_VAR) to specify environment variables in CFLAGS. For example, to include the directory $MY_ENV_VAR/include for compilation, you can specify the CFLAG as -I$::env(MY_ENV_VAR)/include.
  7. Click Remove to delete any files from your project that are not needed or were added by mistake.
  8. Next to the Top Function field, click Browse to list the functions and sub-functions found in the added files.
    The Select Top Function dialog box is opened as shown below. This dialog box lists the functions found in the added files, and lets you specify which of these is the top function for the purposes of HLS.

    Tip: You can simply type the name of top-level function in the available field. However, after source files have been added to the project, the tool lists the available functions for you to choose from.
  9. In the Add/Remove Design Files page, with files added and the top function specified, click Next to proceed.
    In the Add/Remove Testbench Files dialog box, you can add test bench files and other required files to your project, as shown in the following figure.
    Tip: There is no requirement to add a test bench to the project. You can simply click Next to skip this step if you prefer.


  10. As with the C source files, click Add Files to add the test bench. Click Edit CFLAGS or Edit CSIMFLAGS to include any compiler options.
  11. In addition to the C source files, all files read by the test bench must be added to the project. In the example shown in the figure above, the test bench opens file in.dat to supply input stimuli to the design, and reads out.golden.dat to read the expected results. Because the test bench accesses these files, both files must be included in the project.
    Tip: If the test bench files exist in a directory, you can add the entire directory to the project, rather than the individual files, by clicking Add Folder.
  12. Click Next to proceed and the Solution Configuration dialog box is displayed, letting you configure the initial solution for your project.

  13. Specify a Solution Name to collect the directives, the results, and the reports for a specific configuration of the project. Multiple solutions let you create different project configurations to quickly find the best solution.
  14. Under Clock, specify the Period in units of ns, or as a frequency value specified with the MHz suffix (for example, 150 MHz). Refer to Specifying the Clock Frequency for more information.
  15. Specify the Uncertainty used for synthesis as the clock period minus the clock uncertainty. Vitis HLS uses internal models to estimate the delay of the operations for each device. The clock uncertainty value provides a controllable margin to account for any increases in net delays due to RTL logic synthesis, place, and route. Specify as a value in nanoseconds (ns), or as a percentage of the clock period. The default clock uncertainty is 12.5% of the clock period.
  16. Complete Part Selection for your project by clicking the browse button () to display the Device Selection Dialog box, as shown below.

    The Device Selection Dialog box lets you select the device for your project as a part, or as a board, such as an Alveo™ Data Center accelerator card. You can click the Search filter to reduce the number of devices in the device list.

  17. Select the appropriate Flow Target from the drop-down menu to configure the project and enable the output of the synthesized project as described in Vitis HLS Process Overview. By specifying the Flow Target, you can configure the HLS tool to develop kernels for the Vitis application acceleration development flow, or RTL IP for use in the Vivado Design Suite.
  18. Click Finish to create and open the new Vitis HLS project as shown in the following figure.

By default the Vitis HLS IDE initially displays four panes:

  • In the upper left-hand side, the Explorer view lets you navigate through the project hierarchy. A similar hierarchy exists in the project directory on the disk.
  • In the center, the Information area displays report summaries and open files. Files can be opened by double-clicking them in the Explorer view.
  • At the bottom, the Console view displays the output when Vitis HLS is running synthesis or simulation.
  • In the lower left-hand side, the Flow Navigator view which provides access to commands and processes as described in Using the Flow Navigator to take your source code through simulation, synthesis, and exported output.
  • Though not displayed by default, when source code is opened in the Information area the Outline and Directive views are displayed on the right-side, and show information related to the hierarchy of the code.

In addition to the views displayed by default, there are additional views that are opened by launching specific processes such as C/RTL co-simulation, or opening source files or reports. Additional views can be opened using the Window > Show View command from the main menu.