Default Settings of Vivado/Vitis Flows - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The open_solution target will configure the compiler for either the Vivado IP flow or the Vitis Kernel flow. This will change the default behavior of the tool according to the flow specified. The following table shows the default settings of both flows so that you can quickly determine the differences in the default configuration.

Tip: Beyond the default configuration, there are additional features of the Vitis HLS tool that support one flow, but not the other, or are configured differently between the two flows. Those differences are highlighted throughout this document.
Table 1. Default Configuration
Configuration Vivado Vitis
set_clock_uncertainty 27% 27%
config_compile -pipeline_loops 64 64
config_compile -name_max_length 255 255
config_export -vivado_optimization_level 0 0
config_export -vivado_phys_opt none none
config_rtl -module_auto_prefix true true
config_rtl -register_reset_num 0 3
config_schedule -enable_dsp_full_reg true true
INTERFACE pragma defaults IP mode Kernel mode
config_interface -m_axi_addr64 true true
config_interface -m_axi_latency 0 64
config_interface -m_axi_alignment_byte_size 0 64
config_interface -m_axi_max_widen_bitwidth 0 512
config_interface -default_slave_interface s_axilite s_axilite
config_interface -m_axi_offset slave slave